Chapter 6 S12Z Debug (S12ZDBGV2) Module
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
211
6.4.3.1.2
Data Access Comparator Match
Data access matches are generated when an access occurs at the address contained in the comparator
address register. The match can be qualified by the access data and by the access type (read/write). The
breakpoint occurs a maximum of 2 instructions after the access in the CPU flow. Note, if a COF occurs
between access and breakpoint, the opcode address of the breakpoint can be elsewhere in the memory map.
Opcode fetches are not classed as data accesses. Thus data access matches are not possible on opcode
fetches.
6.4.3.2
External Event
The DBGEEV input signal can force a state sequencer transition, independent of internal comparator
matches. The DBGEEV is an input signal mapped directly to a device pin and configured by the EEVE
field in DBGC1. The external events can change the state sequencer state, or force a trace buffer entry, or
gate trace buffer entries.
If configured to change the state sequencer state, then the external match is mapped to DBGSCRx bits
C3SC[1:0]. In this configuration, internal comparator channel3 is de-coupled from the state sequencer but
can still be used for timestamps. The DBGEFR bit EEVF is set when an external event occurs.
6.4.3.3
Setting The TRIG Bit
Independent of comparator matches it is possible to initiate a tracing session and/or breakpoint by writing
the TRIG bit in DBGC1 to a logic “1”. This forces the state sequencer into the Final State. If configured
for End aligned tracing or for no tracing, the transition to Final State is followed immediately by a
transition to State0. If configured for Begin- or Mid Aligned tracing, the state sequencer remains in Final
State until tracing is complete, then it transitions to State0.
Breakpoints, if enabled, are issued on the transition to State0.
6.4.3.4
Profiling Trace Buffer Overflow Event
During code profiling a trace buffer overflow forces the state sequencer into the disarmed State0 and, if
breakpoints are enabled, issues a breakpoint request to the CPU.
6.4.3.5
Event Priorities
If simultaneous events occur, the priority is resolved according to
. Lower priority events are
suppressed. It is thus possible to miss a lower priority event if it occurs simultaneously with an event of a
higher priority. The event priorities dictate that in the case of simultaneous matches, the match on the
higher comparator channel number (3,2,1,0) has priority.
If a write access to DBGC1 with the ARM bit position set occurs simultaneously to a hardware disarm
from an internal event, then the ARM bit is cleared due to the hardware disarm.
Table 6-45. Event Priorities
Priority
Source
Action
Highest
TB Overflow
Immediate force to state 0, generate breakpoint and terminate tracing
