Chapter 4 Interrupt (S12ZINTV0)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
129
•
One I-bit maskable interrupt vector request associated with IRQ (at address vector base
0x0001D4).
•
up to 113 additional I-bit maskable interrupt vector requests (at addresses vector base
+ 0x000010
.. vector base + 0x0001D0).
•
Each I-bit maskable interrupt request has a configurable priority level.
•
I-bit maskable interrupts can be nested, depending on their priority levels.
•
Wakes up the system from stop or wait mode when an appropriate interrupt request occurs or
whenever XIRQ is asserted, even if X interrupt is masked.
4.1.3
Modes of Operation
•
Run mode
This is the basic mode of operation.
•
Wait mode
In wait mode, the INT module is capable of waking up the CPU if an eligible CPU exception
occurs. Please refer to
Section 4.5.3, “Wake Up from Stop or Wait Mode”
for details.
•
Stop Mode
In stop mode, the INT module is capable of waking up the CPU if an eligible CPU exception
occurs. Please refer to
Section 4.5.3, “Wake Up from Stop or Wait Mode”
for details.
4.1.4
Block Diagram
shows a block diagram of the INT module.
