Freescale Semiconductor MC9S12ZVHL32, Reference Manual

Page: 106 / 874

Chapter 2 Port Integration Module (S12ZVHYPIMV1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
106 Freescale Semiconductor
2.3.2.19 Port Interrupt Flag Register
2.3.2.20 Port Slew Rate Register
Address 0x02C7 PIFT
0x02D7 PIFS
0x028F PIFADL
Access: User read/write
(1)
1. Read: Anytime
Write: Anytime
7 6 5 4 3 2 1 0
R
PIFx7 PIFx6 PIFx5 PIFx4 PIFx3 PIFx2 PIFx1 PIFx0
W
Reset 0 0 0 0 0 0 0 0
Figure 2-21. Port Interrupt Flag Register
Table 2-19. Port Interrupt Flag Register Field Descriptions
Field Description
7-0
PIFx
Port Interrupt Flag — Signal pin event
The flag asserts after a valid active edge was detected on the related pin (see Section 2.4.4, “Pin interrupts and
Wakeup“ ”). This can be a rising or a falling edge based on the state of the polarity select register.
Writing a logic “1” to the corresponding bit field clears the flag.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set)
0 No active edge occurred
Address 0x035E SRRU Access: User read/write
(1)
1. Read: Anytime
Write: Anytime
7 6 5 4 3 2 1 0
R
SRRx7 SRRx6 SRRx5 SRRx4 SRRx3 SRRx2 SRRx1 SRRx0
W
Reset 0 0 0 0 0 0 0 0
Figure 2-22. Port Slew Rate Register
Table 2-20. Port Interrupt Flag Register Field Descriptions
Field Description
7-0
SRRx
Port Slew Rate — Slew Rate control
(1)
1 Enable the slew rate control and disable the digital input buffer
0 Disable the slew rate control and enable the digital input buffer