Chapter 2 Port Integration Module (S12ZVHYPIMV1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
112
Freescale Semiconductor
Both interrupts are capable to wake-up the device from stop mode. Means for glitch filtering are not
provided on these pins.
2.4.4
Pin interrupts and Wakeup
Ports S, T and AD offer pin interrupt and key-wakeup capability. The related interrupt enable (PIE) as well
as the sensitivity to rising or falling edges (PPS) can be individually configured on per-pin basis. All
bits/pins in a port share the same interrupt vector. Interrupts can be used with the pins configured as inputs
or outputs.
An interrupt is generated when a bit in the port interrupt flag (PIF) and its corresponding port interrupt
enable (PIE) are both set. The pin interrupt feature is also capable to wake up the CPU when it is in stop
or wait mode(key-wakeup).
A digital filter on each pin prevents short pulses from generating an interrupt. A valid edge on an input is
detected if 4 consecutive samples of a passive level are followed by 4 consecutive samples of an active
level. Else the sampling logic is restarted.
In run and wait mode the filters are continuously clocked by the bus clock. Pulses with a duration of
t
PULSE
< n
P_MASK
/f
bus
are assuredly filtered out while pulses with a duration of t
PULSE
> n
P_PASS
/f
bus
guarantee a pin interrupt.
In stop mode the filter clock is generated by an RC-oscillator. The minimum pulse length varies over
process conditions, temperature and voltage(
). Pulses with a duration of t
PULSE
< t
P_MASK
are
assuredly filtered out while pulses with a duration of t
PULSE
> t
P_PASS
guarantee a wakeup event.
Please refer to the appendix table “Pin Interrupt Characteristics” for pulse length limits.
To maximize current saving the RC oscillator is active only if the following condition is true on any
individual pin:
Sample count <= 4 (at active or passive level) and interrupt flag not set (PIF[x]=0).
Figure 2-25. Interrupt Glitch Filter (here: active low level selected)
Glitch, filtered out, no interrupt flag set
Valid pulse, interrupt flag set
uncertain
t
P_MASK
t
P_PASS
