Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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Chapter 2 Port Integration Module (S12ZVHYPIMV1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor 101
2.3.2.13 Data Direction Register
NOTE
Due to internal synchronization circuits, it can take up to two bus clock
cycles until the correct value is read on port data and port input registers,
when changing the data direction register.
The general-purpose data direction configuration can be overruled by an enabled peripheral function
shared on the same pin (
Table 2-22 ). If more then one peripheral function is available and enabled at the
same time, the highest ranked module according the predefined priority scheme in Table 2-1 will take
precedence on the pin.
Address 0x0224 DDRA
0x0225 DDRB
0x0244 DDRC
0x0245 DDRD
0x0264 DDRE
0x0265 DDRF
0x0285 DDRADL
0x02C2 DDRT
0x02D2 DDRS
0x02F2 DDRP
0x0302 DDRH
0x0312 DDRJ
0x0322 DDRG
0x0352 DDRU
Access: User read/write
(1)
1. Read: Anytime
Write: Anytime
7 6 5 4 3 2 1 0
R
DDRx7 DDRx6 DDRx5 DDRx4 DDRx3 DDRx2 DDRx1 DDRx0
W
Reset 0 0 0 0 0 0 0 0
Figure 2-15. Data Direction Register
Table 2-13. Data Direction Register Field Descriptions
Field Description
7-0
DDRx
Data Direction — Select general-purpose data direction
This bit determines whether the pin is a general-purpose input or output.
1 Associated pin is configured as output
0 Associated pin is configured as input