Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V5)
S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05
238
Freescale
Semiconductor
This supply domain is monitored by the Low Voltage Reset circuit.
VDDX has to be connected externally to VDDA.
7.2.6
BCTL — Base Control Pin for external PNP
BCTL is the ballast connection for the on chip voltage regulator. It provides the base current of an external
JT (PNP) of the VDDX and VDDA supplies. An additional 1K
resistor between emitter and base of the
BJT is required. See the device specification if this pin is available on this device.
7.2.7
VSS — Core Logic Ground Pin
VSS is the core logic supply return pin. It must be grounded.
7.2.8
VDD — Internal Regulator Output Supply (Core Logic)
Node VDD is a device internal supply output of the voltage regulator that provides the power supply for
the internal core logic.
This supply domain is monitored by the Low Voltage Reset circuit and The Power On Reset circuit.
7.2.9
VDDF — Internal Regulator Output Supply (NVM Logic)
Node VDDF is a device internal supply output of the voltage regulator that provides the power supply for
the NVM logic.
This supply domain is monitored by the Low Voltage Reset circuit.
7.2.10
API_EXTCLK — API external clock output pin
This pin provides the signal selected via APIES and is enabled with APIEA bit. See the device
specification if this clock output is available on this device and to which pin it might be connected.
7.2.11
TEMPSENSE — Internal Temperature Sensor Output Voltage
Depending on the VSEL setting either the voltage level generated by the temperature sensor or the VREG
bandgap voltage is driven to a special channel input of the ADC Converter. See device level specification
for connectivity of ADC special channels.
