Chapter 2 Port Integration Module (S12ZVHYPIMV1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
111
2.4.2.8
Interrupt flag register (PIFx)
If the pin is used as an interrupt input this register holds the interrupt flag after a valid pin event.
2.4.2.9
Digital input enable register (DIENADx)
This register controls the digital input buffer. If DIENADx is set to logic level “1”, then it will enable the
digital input buffer.
2.4.2.10
Slew rate register (SRRx)
This register selects the slew rate function on the motor pad. It also controls the digital input buffer. If
SRRx is set to logic level “1”, then it will disable the digital input buffer.
2.4.2.11
Module routing register (MODRRx)
Routing registers allow software re-configuration of specific peripheral inputs and outputs:
•
MODRR0 supports CAN0 rerouting
•
MODRR1 supports PWM channel rerouting
•
MODRR2 supports TIM1IC0, IIC0 and SCI1 rerouting
•
MODRR3 supports LINPHY0 and SCI0 rerouting
2.4.3
Interrupts
This section describes the interrupts generated by the PIM and their individual sources. Vector addresses
and interrupt priorities are defined at MCU level.
2.4.3.1
XIRQ, IRQ Interrupts
The XIRQ pin allows requesting non-maskable interrupts after reset initialization. During reset, the X bit
in the condition code register is set and any interrupts are masked until software enables them.
The IRQ pin allows requesting asynchronous interrupts. The interrupt input is disabled out of reset. To
enable the interrupt the IRQCR[IRQEN] bit must be set and the I bit cleared in the condition code register.
The interrupt can be configured for level-sensitive or falling-edge-sensitive triggering. If IRQCR[IRQEN]
is cleared while an interrupt is pending, the request will deassert.
Table 2-23. PIM Interrupt Sources
Module Interrupt Sources
Local Enable
XIRQ
None
IRQ
IRQCR[IRQEN]
Port S pin interrupt
PIES[PIES7-PIES0]
Port T pin interrupt
PIET[PIET7-PIET0]
Port AD pin interrupt
PIEADL[PIEADL7-PIEADL0]
