Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V5)
S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05
Freescale Semiconductor
259
7.3.2.13
S12CPMU_UHV_V5 COP Timer Arm/Reset Register (CPMUARMCOP)
This register is used to restart the COP time-out period.
Read: Always reads $00
Write: Anytime
When the COP is disabled (CR[2:0] = “000”) writing to this register has no effect.
When the COP is enabled by setting CR[2:0] nonzero, the following applies:
Writing any value other than $55 or $AA causes a COP reset. To restart the COP time-out period
write $55 followed by a write of $AA. These writes do not need to occur back-to-back, but the
sequence ($55, $AA) must be completed prior to COP end of time-out period to avoid a COP reset.
Sequences of $55 writes are allowed. When the WCOP bit is set, $55 and $AA writes must be done
in the last 25% of the selected time-out period; writing any value in the first 75% of the selected
period will cause a COP reset.
7.3.2.14
H
igh
T
emperature
Control Register (CPMUHTCTL)
The CPMUHTCTL register configures the temperature sense features.
Read: Anytime
Write: VSEL, HTE, HTIE and HTIF are write anytime, HTDS is read only
Module Base + 0x000F
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W ARMCOP-Bit
7
ARMCOP-Bit
6
ARMCOP-Bit
5
ARMCOP-Bit
4
ARMCOP-Bit
3
ARMCOP-Bit
2
ARMCOP-Bit
1
ARMCOP-Bit
0
Reset
0
0
0
0
0
0
0
0
Figure 7-16. S12CPMU_UHV_V5 CPMUARMCOP Register
Module Base + 0x0010
7
6
5
4
3
2
1
0
R
0
0
VSEL
0
HTE
HTDS
HTIE
HTIF
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-17. High Temperature Control Register (CPMUHTCTL)
