Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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Chapter 19 Simple Sound Generator (SSGV1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor 661
19.3.2.3 SSG Clock Prescaler Register (SSGPS)
SSGPS is a 11 bit prescaler register. For the 32MHz input bus clock source, the frequency range of
encoding amplitude waveform is from 15.625KHz to 125KHz, so the divided clock frequency is as
Table 19-5 .
Read: Anytime
Write: Anytime
Module Base + 0x0002
7 6 5 4 3 2 1 0
R 0 0 0 0 0
PS10 PS9 PS8
W
Reset 0 0 0 0 0 0 0 0
Figure 19-5. SSG Clock Prescaler Register (SSGPSH)
Module Base + 0x0003
7 6 5 4 3 2 1 0
R
PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0
W
Reset 0 0 0 0 0 0 0 0
Figure 19-6. SSG Clock Prescaler Register (SSGPSL)
Table 19-4. SSGPS Field Descriptions
Field Description
10–0
PS[10:0]
SSG Clock Prescaler Register Bits —
The input clock will be divided by SSGPS+1. This divided signal will be used as tone counter clock. Also it will
decide the amplitude of the PWM cycle period.
Table 19-5. Prescaler Clock Divider
Divided Clock Frequency From
32MHz Clock Source
Divide Ratio SSGPS[10:0]
125KHz 256 0xFF
124.514KHz 257 0x100
124.031KHz 258 0x101
123.552KHz~15.633KHz 259~2047 0x102~0x7FE
15.625KHz 2048 0x7FF