Chapter 18 Real-Time Counter With Calendar (RTCV2)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
645
18.4.4 RTC Control Register 4 (RTCCTL4)
The RTCCTL4 contains the interrupt enable bits for RTC interrupt functions.
Table 18-5. RTCCTL3 Field Descriptions
Field
Description
7:6
RTCWE[1:0]
RTC Module Write Enable
— These two write-only bits control the write-protect function of several
RTC registers and bits. After a reset, write-protect is disabled, allowing full write access to RTC registers and
bits. These two bits always read as 0.
To enable write-protect, perform the following sequence:
1. Write %10 to RTCWE[1:0] bits
2. Write %10 to RTCWE[1:0] bits
To disable write-protect, perform the following sequence:
1. Write %00 to RTCWE[1:0] bits
2. Write %01 to RTCWE[1:0] bits
3. Write %11 to RTCWE[1:0] bits
4. Write %10 to RTCWE[1:0] bits
To disable write-protect from an unsure protection state, first perform the enable write-protect sequence, fol-
lowed by the disable write protect sequence.
3
FRZ
RTC Stop in Freeze Mode
— The read/write bit decide the RTC behavioral during Freeze mode.
0 RTC run during freeze mode.
1 RTC stop during freeze mode.
1
CALS
RTC Calibration Clock Selection
— The read/write bit enables the clock calibration source selection.
0 RTCCLK is output to CALCLK.
1 1HZ compensation clock is output to CALCLK.
7
6
5
4
3
2
1
0
R
0
0
HRIE
MINIE
SECIE
COMPIE
0
TB0IE
W
Reset:
0
0
0
0
0
0
0
0
Figure 18-5. RTC Control Register 4 (RTCCTL4)
Table 18-6. RTCCTL4 Field Descriptions
Field
Description
5
HRIE
Hour Interrupt Enable
— This read/write bit enables hour interrupts. If HRIE is set, then an interrupt is
generated when HRF is set.
0 Hour interrupt request is disabled.
1 Hour interrupt request is enabled.
4
MINIE
Minute Interrupt Enable
— This read/write bit enables minute interrupts. If MINIE is set, then an interrupt is
generated when MINF is set.
0 Minute interrupt request is disabled.
1 Minute interrupt request is enabled.
3
SECIE
Second Interrupt Enable
— This read/write bit enables second interrupts. If SECIE is set, then an interrupt is
generated when SECF is set.
0 Second interrupt request is disabled.
1 Second interrupt request is enabled.
