Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
354
Freescale Semiconductor
The four bits of register ADCFLWCTL reflect the captured request and status of the four internal interface
Signals (LoadOK, Trigger, Restart, and Seq_abort; see also
) if access configuration is set
accordingly and indicate event progress (when an event is processed and when it is finished).
Conversion flow error situations are captured by corresponding interrupt flags in the ADCEIF register.
There are two conversion flow control modes (Restart Mode, Trigger Mode). Each mode causes a certain
behavior of the conversion flow control bits which can be selected according to the application needs.
Please refer to
Section 10.4.2.1, “ADC Control Register 0 (ADCCTL_0)
conversion flow control Mode Configurations
for more information regarding conversion flow control.
Because internal components of the ADC are turned on/off with bit ADC_EN, the ADC requires a
recovery time period (t
REC
) after ADC is enabled until the first conversion can be launched via a trigger.
When bit ADC_EN gets cleared (transition from 1’b1 to 1’b0) any ongoing conversion sequence will be
aborted and pending results, or the result of current conversion, gets discarded (not stored). The ADC
cannot be re-enabled before any pending action or action in process is finished respectively aborted, which
could take up to a maximum latency time of t
DISABLE
(see device reference manual for more details).
