Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
407
If signal Restart is asserted before signal LoadOK is set the conversion starts from top of
currently active CSL at the next Trigger Event (no exchange of CSL list).
If signal Restart is asserted after or simultaneously with signal LoadOK the conversion
starts from top of the other CSL at the next Trigger Event (CSL is switched) if CSL is
configured for double buffer mode.
•
Sequence Abort Event
Internal Interface Signal: Seq_Abort
Corresponding Bit Name: SEQA
–
Function:
Abort any possible ongoing conversion at next conversion boundary and abort current
conversion sequence and active CSL
–
Requested by:
- Positive edge of internal interface signal Seq_Abort
- Write Access via data bus to set control bit SEQA
–
When finished:
This bit gets cleared when an ongoing conversion is finished and the result is stored and/or
an ongoing conversion sequence is aborted and current active CSL is aborted (ADC idle,
RVL done)
–
Mandatory Requirement:
- In all ADC conversion flow control modes bit SEQA can only be set if:
* ADC not idle (a conversion or conversion sequence is ongoing)
* ADC idle but RVL done condition not reached
The RVL done condition is not reached if:
* An “End Of List” command type has not been executed
* A Sequence Abort Event has not been executed (bit SEQA not already set)
- In all ADC conversion flow control modes a Sequence Abort Event can be issued at any
time
- In ADC conversion flow control mode “Restart Mode” after a conversion sequence abort
request has been executed it is mandatory to set bit RSTA. If a Trigger Event occurs before
a Restart Event is executed (bit RSTA set and cleared by hardware), bit TRIG is set, error
flag TRIG_EIF is set, and the ADC can only be continued by a Soft-Reset. After the Restart
Event the ADC accepts new Trigger Events (bit TRIG set) and begins conversion from top
of the currently active CSL.
- In ADC conversion flow control mode “Restart Mode” after a Sequence Abort Event has
been executed, a Restart Event causes only the RSTA bit being set. The ADC executes a
Restart Event only.
– In both conversion flow control modes (“Restart Mode” and “Trigger Mode”) when
conversion flow control bit RSTA gets set automatically bit SEQA gets set when the ADC
has not reached one of the following scenarios:
* An “End Of List” command type has been executed or is about to be executed
* A Sequence Abort request is about to be executed or has been executed.
In case bit SEQA is set automatically the Restart error flag RSTA_EIF is set to indicate an
unexpected Restart Request.
