Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
420
Freescale Semiconductor
10.8.10 Fully Timing Controlled Conversion
As described previously, in “Trigger Mode” a Restart Event automatically causes a trigger. To have full
and precise timing control of the beginning of any conversion/sequence the “Restart Mode” is available.
In “Restart Mode” a Restart Event does not cause a Trigger automatically; instead, the Trigger must be
issued separately and with correct timing, which means the Trigger is not allowed before the Restart Event
(conversion command loading) is finished (bit RSTA=1’b0 again). The time required from Trigger until
sampling phase starts is given (refer to
Section 10.4.2.6, “ADC Conversion Flow Control Register
, Timing considerations) and hence timing is fully controllable by the application.
Additionally, if a Trigger occurs before a Restart Event is finished, this causes the TRIG_EIF flag being
set. This allows detection of false flow control sequences.
Figure 10-44. Conversion Flow Control Diagram — Fully Timing Controlled Conversion (with Stop Mode)
Unlike the Stop Mode entry shown in
and
it is recommended to issue the Stop
Mode at sequence boundaries (when ADC is idle and no conversion/conversion sequence is ongoing).
Any of the Conversion flow control application use cases described above (Continuous, Triggered, or
Fully Timing Controlled Conversion) can be used with CSL single buffer mode or with CSL double buffer
mode. If using CSL double buffer mode, CSL swapping is performed by issuing a Restart Event with bit
LDOK set.
CSL_0
Active
AN3 AN1 AN4 IN5
any
Restart
Event
EOS
AN21AN0 AN4 IN3
EOS
AN6 AN1
Stop Mode request,
Automatic Sequence Abort
Event
Idle
Stop Mode
entry
Wake-up
Event with
Idle
AUT_RSTA
Active
AN3 AN1 AN4
Abort
Sequence_0
Sequence_1
Trigger
Trigger
EOS
Sequence_0
Sequence_2
AN5 AN2 AN0
Sequence_1
Trigger
Begin from top of current CSL
Trigger
conversion command
load phase
t
