Chapter 19 Simple Sound Generator (SSGV1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
657
19.2.2
SGA
Encoded amplitude output signal of SSG.
19.3
Memory Map and Register Definition
19.3.1
Module Memory Map
This section describes the content of the registers in the SSG module. The base address of the SSG module
is determined at the MCU level when the MCU is defined. The register decode map is fixed and begins at
the first address of the module address offset. The figure below shows the registers associated with the
SSG and their relative offset from the base address. The register detail description follows the order they
appear in the register map.
Reserved bits within a register will always read as 0 and the write will be unimplemented. Unimplemented
functions are indicated by shading the bit.
NOTE
Register Address = Base A Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
19.3.2
Register Descriptions
This section describes in detail all the registers and register bits in the SSG module.
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x0000
SSGCR
R
SSGE
0
0
0
0
OMS
RDR
STP
W
0x0001
SSGADC
R
ADE
0
0
0
0
ADM[1:0]
ADS
W
0x0002
SSGPSH
R
0
0
0
0
0
PS10
PS9
PS8
W
0x0003
SSGPSL
R
PS7
PS6
PS5
PS4
PS3
PS2
PS1
PS0
W
= Unimplemented or Reserved
Figure 19-2. The SSG Register Summary (Sheet 1 of 3)
