Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V5)
S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05
252 Freescale Semiconductor
7.3.2.9 S12CPMU_UHV_V5 RTI Control Register (CPMURTI)
This register selects the time-out period for the Real Time Interrupt.
The clock source for the RTI is either IRCCLK or OSCCLK depending on the setting of the RTIOSCSEL
bit. In Stop Mode with PSTP=1 (Pseudo Stop Mode) and RTIOSCSEL=1 the RTI continues to run, else
the RTI counter halts in Stop Mode.
Read: Anytime
Write: Anytime
NOTE
A write to this register starts the RTI time-out period. A change of the
RTIOSCSEL bit (writing a different value or loosing UPOSC status)
re-starts the RTI time-out period.
Module Base + 0x000B
7 6 5 4 3 2 1 0
R
RTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0
W
Reset 0 0 0 0 0 0 0 0
Figure 7-12. S12CPMU_UHV_V5 RTI Control Register (CPMURTI)
Table 7-11. CPMURTI Field Descriptions
Field Description
7
RTDEC
Decimal or Binary Divider Select Bit — RTDEC selects decimal or binary based prescaler values.
0 Binary based divider value. See Table 7-12
1 Decimal based divider value. See Table 7-13
6–4
RTR[6:4]
Real Time Interrupt Prescale Rate Select Bits — These bits select the prescale rate for the RTI.See Table 7-12
and Table 7-13 .
3–0
RTR[3:0]
Real Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to
provide additional granularity. Table 7-12 and Table 7-13 show all possible divide values selectable by the
CPMURTI register .