Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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Chapter 21 64 KB Flash Module (S12ZFTMRZ64K2KV2)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor 705
21.3.2.8 Flash Error Status Register (FERSTAT)
The FERSTAT register reflects the error status of internal Flash operations.
All flags in the FERSTAT register are readable and only writable to clear the flag.
2
RSVD
Reserved Bit — This bit is reserved and always reads 0
.
1–0
MGSTAT[1:0]
Memory Controller Command Completion Status Flag — One or more MGSTAT flag bits are set if an error
is detected during execution of a Flash command or during the Flash reset sequence. The MGSTAT bits are
cleared automatically at the start of the execution of a Flash command. See
Section 21.4.7, “Flash Command
Description ,” and Section 21.6, “Initialization ” for details.
Offset Module Base + 0x0007
7 6 5 4 3 2 1 0
R 0 0 0 0 0 0
DFDF SFDIF
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 21-12. Flash Error Status Register (FERSTAT)
Table 21-18. FERSTAT Field Descriptions
Field Description
1
DFDF
Double Bit Fault Detect Flag — The setting of the DFDF flag indicates that a double bit fault was detected in
the stored parity and data bits during a Flash array read operation or that a Flash array read operation returning
invalid data was attempted on a Flash block that was under a Flash command operation.
(1)
The DFDF flag is
cleared by writing a 1 to DFDF. Writing a 0 to DFDF has no effect on DFDF.
(2)
0 No double bit fault detected
1 Double bit fault detected or a Flash array read operation returning invalid data was attempted while command
running. See Section 21.4.3, “Flash Block Read Access ” for details
1. In case of ECC errors the corresponding flag must be cleared for the proper setting of any further error, i.e. any new error will
only be indicated properly when DFDF and/or SFDIF are clear at the time the error condition is detected.
2. There is a one cycle delay in storing the ECC DFDF and SFDIF fault flags in this register. At least one NOP is required after
a flash memory read before checking FERSTAT for the occurrence of ECC errors.
0
SFDIF
Single Bit Fault Detect Interrupt Flag — With the IGNSF bit in the FCNFG register clear, the SFDIF flag
indicates that a single bit fault was detected in the stored parity and data bits during a Flash array read operation
or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash
command operation. The SFDIF flag is cleared by writing a 1 to SFDIF. Writing a 0 to SFDIF has no effect on
SFDIF.
0 No single bit fault detected
1 Single bit fault detected and corrected or a Flash array read operation returning invalid data was attempted
while command running
Table 21-17. FSTAT Field Descriptions (continued)
Field Description