Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V5)
S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05
Freescale Semiconductor
231
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Frequency trimming
(A factory trim value for 1MHz is loaded from Flash Memory into the CPMUIRCTRIMH and
CPMUIRCTRIML registers after reset, which can be overwritten by application if required)
•
Temperature Coefficient (TC) trimming.
(A factory trim value is loaded from Flash Memory into the IRCTRIM register to turn off TC
trimming after reset. Application can trim the TC if required by overwriting the IRCTRIM
register).
Other features of the S12CPMU_UHV_V5 include
•
Oscillator clock monitor to detect loss of crystal
•
Autonomous periodical interrupt (API)
•
Bus Clock Generator
— Clock switch to select either PLLCLK or external crystal/resonator based Bus Clock
— PLLCLK divider to adjust system speed
•
System Reset generation from the following possible sources:
— Power-on reset (POR)
— Low-voltage reset (LVR)
— COP system watchdog, COP reset on time-out, windowed COP
— Loss of oscillation (Oscillator clock monitor fail)
— Loss of PLL clock (PLL clock monitor fail)
— External pin RESET
