Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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Chapter 15 Liquid Crystal Display (LCD40F4BV3) Block Description
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor 581
15.4 Functional Description
This section provides a complete functional description of the LCD40F4BV3 block, detailing the
operation of the design from the end user perspective in a number of subsections.
15.4.1 LCD Driver Description
15.4.1.1 Frontplane, Backplane, and LCD System During Reset
During a reset the following conditions exist:
• The LCD40F4BV3 system is configured in the default mode, 1/4 duty and 1/3 bias, that means all
backplanes are used.
• All frontplane enable bits, FP[39:0]EN are cleared and the ON/OFF control for the display, the
LCDEN bit is cleared, thereby forcing all frontplane and backplane driver outputs to the high
impedance state. The MCU pin state during reset is defined by the port integration module (PIM).
15.4.1.2 LCD Clock and Frame Frequency
The frequency of the source clock (
RTCCLK
) and divider determine the LCD clock frequency. The divider
is set by the LCD clock prescaler bits, LCLK[1:0], in the LCD control register 0 (LCDCR0). Table 15-8
shows the LCD clock and frame frequency for some multiplexed mode at
RTCCLK
= 32768Hz, 32000Hz,
and 64000Hz.
Table 15-7. LCD RAM Field Descriptions
Field Description
39:0
3:0
FP[39:0]
BP[3:0]
LCD Segment ON — The FP[39:0]BP[3:0] bit displays (turns on) the LCD segment connected between FP[39:0]
and BP[3:0].
0 LCD segment OFF
1 LCD segment ON
Table 15-8. LCD Clock and Frame Frequency
Source clock
Frequency in
Hz
LCD Clock
Prescaler
Divider
LCD Clock
Frequency [Hz]
Frame Frequency [Hz]
LCLK1 LCLK0 1/1 Duty 1/2 Duty 1/3 Duty 1/4 Duty
RTCCLK = 32768
0
0
1
1 0
1
0
1 64
128
256
512
512
256
128
64
512
256
128
64
256
128
64
32
171
85
43
21
128
64
32
16
RTCCLK = 32000
0
0
1
1 0
1
0
1 64
128
256
512
500
250
125
63
500
250
125
63
250
125
63
31
167
83
42
21
125
63
31
16