Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
401
Figure 10-32. Command Sequence List Schema in Single Buffer Mode
While the ADC is enabled, one CSL is active (indicated by bit CSL_SEL) and the corresponding list
should not be modified anymore. At the same time the alternative CSL can be modified to prepare the ADC
for new conversion sequences in CSL double buffered mode. When the ADC is enabled, the command
address registers (ADCCBP, ADCCROFF_0/2, ADCCIDX) are read only and register ADCCIDX is under
control of the ADC.
Memory Map
0x00_0000
Register Space
RAM or NVM Space
RAM or NVM start address
RAM or NVM end address
CSL_0
(active)
(ADCCROFF_0)
(ADC
CSL_SEL = 1’b0 (forced by CSL_BMOD)
ADCCIDX(max))
Note:
Address register names in () are not absolute addresses instead they are a sample offset or sample index
