Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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Chapter 4 Interrupt (S12ZINTV0)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor 131
4.3.2 Register Descriptions
This section describes in address order all the INT module registers and their individual bits.
0x000019 Interrupt Request Configuration Data Register 1
(INT_CFDATA1)
R/W
0x00001A Interrupt Request Configuration Data Register 2
(INT_CFDATA2
R/W
0x00001B Interrupt Request Configuration Data Register 3
(INT_CFDATA3)
R/W
0x00001C Interrupt Request Configuration Data Register 4
(INT_CFDATA4)
R/W
0x00001D Interrupt Request Configuration Data Register 5
(INT_CFDATA5)
R/W
0x00001E Interrupt Request Configuration Data Register 6
(INT_CFDATA6)
R/W
0x00001F Interrupt Request Configuration Data Register 7
(INT_CFDATA7)
R/W
Address
Register
Name
Bit 7 6 5 4 3 2 1 Bit 0
0x000010 IVBR R
IVB_ADDR[15:8]
W
0x000011 R
IVB_ADDR[7:1]
0
W
0x000017 INT_CFADDR R 0
INT_CFADDR[6:3]
0 0 0
W
0x000018 INT_CFDATA0 R 0 0 0 0 0
PRIOLVL[2:0]
W
0x000019 INT_CFDATA1 R 0 0 0 0 0
PRIOLVL[2:0]
W
0x00001A INT_CFDATA2 R 0 0 0 0 0
PRIOLVL[2:0]
W
0x00001B INT_CFDATA3 R 0 0 0 0 0
PRIOLVL[2:0]
W
0x00001C INT_CFDATA4 R 0 0 0 0 0
PRIOLVL[2:0]
W
= Unimplemented or Reserved
Figure 4-2. INT Register Summary
Table 4-3. INT Memory Map