Chapter 6 S12Z Debug (S12ZDBGV2) Module
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
200
Freescale Semiconductor
shows the effect for RWE and RW on the comparison conditions. These bits are ignored if
INST is set, as matches based on instructions reaching the execution stage are data independent.
6.3.2.17
Debug Comparator B Address Register (DBGBAH, DBGBAM, DBGBAL)
Read: Anytime.
Write: If DBG not armed and PTACT is clear.
Table 6-31. Read or Write Comparison Logic Table
RWE Bit
RW Bit
RW Signal
Comment
0
x
0
RW not used in comparison
0
x
1
RW not used in comparison
1
0
0
Write match
1
0
1
No match
1
1
0
No match
1
1
1
Read match
Address: 0x0125, DBGBAH
23
22
21
20
19
18
17
16
R
DBGBA[23:16]
W
Reset
0
0
0
0
0
0
0
0
Address: 0x0126, DBGBAM
15
14
13
12
11
10
9
8
R
DBGBA[15:8]
W
Reset
0
0
0
0
0
0
0
0
Address: 0x0127, DBGBAL
7
6
5
4
3
2
1
0
R
DBGBA[7:0]
W
Reset
0
0
0
0
0
0
0
0
Figure 6-19. Debug Comparator B Address Register
Table 6-32. DBGBAH, DBGBAM, DBGBAL Field Descriptions
Field
Description
23–16
DBGBA
[23:16]
Comparator Address Bits [23:16]
— These comparator address bits control whether the comparator compares
the address bus bits [23:16] to a logic one or logic zero.
0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
15–0
DBGBA
[15:0]
Comparator Address Bits
[15:0]— These comparator address bits control whether the comparator compares
the address bus bits [15:0] to a logic one or logic zero.
0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
