Chapter 21 64 KB Flash Module (S12ZFTMRZ64K2KV2)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
703
21.3.2.6
Flash Error Configuration Register (FERCNFG)
The FERCNFG register enables the Flash error interrupts for the FERSTAT flags.
All assigned bits in the FERCNFG register are readable and writable.
1
FDFD
Force Double Bit Fault Detect
— The FDFD bit allows the user to simulate a double bit fault during Flash array
read operations. The FDFD bit is cleared by writing a 0 to FDFD.
0 Flash array read operations will set the DFDF flag in the FERSTAT register only if a double bit fault is detected
1 Any Flash array read operation will force the DFDF flag in the FERSTAT register to be set (see
)
0
FSFD
Force Single Bit Fault Detect
—
The FSFD bit allows the user to simulate a single bit fault during Flash array
read operations and check the associated interrupt routine. The FSFD bit is cleared by writing a 0 to FSFD.
0 Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected
1 Flash array read operation will force the SFDIF flag in the FERSTAT register to be set (see
)
and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set (see
)
Table 21-15. Flash Wait-States control
WSTAT[1:0]
Wait-State configuration
00
ENABLED, maximum number of cycles
(1)
1. Reset condition. For a target of 100MHz core frequency /
50MHz bus frequency the maximum number required is 1
cycle.
01
reserved
(2)
2. Value will read as 01 or 10, as written. In the current
implementation the Flash will behave the same as 00 (wait-
states enabled, maximum number of cycles).
10
reserved
11
DISABLED
Offset Module Base + 0x0005
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
SFDIE
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 21-10. Flash Error Configuration Register (FERCNFG)
Table 21-14. FCNFG Field Descriptions (continued)
Field
Description
