Chapter 4 Interrupt (S12ZINTV0)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
138
Freescale Semiconductor
4.4.6
Interrupt Vector Table Layout
The interrupt vector table contains 128 entries, each 32 bits (4 bytes) wide. Each entry contains a 24-bit
address (3 bytes) which is stored in the 3 low-significant bytes of the entry. The content of the most
significant byte of a vector-table entry is ignored.
illustrates the vector table entry format.
Figure 4-13. Interrupt Vector Table Entry
4.5
Initialization/Application Information
4.5.1
Initialization
After system reset, software should:
•
Initialize the interrupt vector base register if the interrupt vector table is not located at the default
location (0xFFFE00–0xFFFFFB).
•
Initialize the interrupt processing level configuration data registers (INT_CFADDR,
INT_CFDATA0–7) for all interrupt vector requests with the desired priority levels. It might be a
good idea to disable unused interrupt requests.
•
Enable I-bit maskable interrupts by clearing the I-bit in the CCW.
•
Enable the X-bit maskable interrupt by clearing the X-bit in the CCW (if required).
4.5.2
Interrupt Nesting
The interrupt request priority level scheme makes it possible to implement priority based interrupt request
nesting for the I-bit maskable interrupt requests.
•
I-bit maskable interrupt requests can be interrupted by an interrupt request with a higher priority,
so that there can be up to seven nested I-bit maskable interrupt requests at a time (refer to
for an example using up to three nested interrupt requests).
(Vector base + 0x0001E8)
Machine exception vector request
(Vector base + 0x0001E4)
Reserved
(Vector base + 0x0001E0)
Reserved
(Vector base + 0x0001DC)
Spurious interrupt
(Vector base + 0x0001D8)
XIRQ interrupt request
(Vector base + 0x0001D4)
IRQ interrupt request
(Vector base + 0x000010
..
Vector base + 0x0001D0)
Device specific I-bit maskable interrupt sources (priority determined by the associated
configuration registers, in descending order)
1. 24 bits vector address based
Bits [31:24]
[23:0]
(unused)
ISR Address
Table 4-8. Exception Vector Map and Priority
Vector Address
(1)
Source
