Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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Chapter 6 S12Z Debug (S12ZDBGV2) Module
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
212 Freescale Semiconductor
6.4.4 State Sequence Control
Figure 6-26. State Sequencer Diagram
The state sequencer allows a defined sequence of events to provide a breakpoint and/or a trigger point for
tracing of data in the trace buffer. When the DBG module is armed by setting the ARM bit in the DBGC1
register, the state sequencer enters State1. Further transitions between the states are controlled by the state
control registers and depend upon event occurrences (see
Section 6.4.3 ). From Final State the only
permitted transition is back to the disarmed State0. Transition between the states 1 to 3 is not restricted.
Each transition updates the SSF[2:0] flags in DBGSR accordingly to indicate the current state. If
breakpoints are enabled, then an event based transition to State0 generates the breakpoint request. A
transition to State0 resulting from writing “0” to the ARM bit does not generate a breakpoint request.
6.4.4.1 Final State
On entering Final State a trigger may be issued to the trace buffer according to the trigger position control
as defined by the TALIGN field (see
Section 6.3.2.3” ).
If tracing is enabled and either Begin or Mid aligned triggering is selected, the state sequencer remains in
Final State until completion of the trace. On completion of the trace the state sequencer returns to State0
and the debug module is disarmed; if breakpoints are enabled, a breakpoint request is generated.
If tracing is disabled or End aligned triggering is selected, then when the Final State is reached the state
sequencer returns to State0 immediately and the debug module is disarmed. If breakpoints are enabled, a
breakpoint request is generated on transitions to State0.
TRIG Force immediately to final state
DBGEEV Force to next state as defined by state control registers (EEVE=2’b10)
Match3 Force to next state as defined by state control registers
Match2 Force to next state as defined by state control registers
Match1 Force to next state as defined by state control registers
Lowest Match0 Force to next state as defined by state control registers
Table 6-45. Event Priorities
State1
Final State
State3
ARM = 1
State2
State 0
(Disarmed)