Freescale Semiconductor MC9S12ZVHL32, Reference Manual

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Chapter 6 S12Z Debug (S12ZDBGV2) Module
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor 187
6.3.2.2 Debug Control Register2 (DBGC2)
Read: Anytime.
Write: Anytime the module is disarmed and PTACT is clear.
This register configures the comparators for range matching.
Address: 0x0101
7 6 5 4 3 2 1 0
R 0 0 0 0
CDCM ABCM
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 6-4. Debug Control Register2 (DBGC2)
Table 6-5. DBGC2 Field Descriptions
Field Description
3–2
CDCM[1:0]
C and D Comparator Match Control — These bits determine the C and D comparator match mapping as
described in Table 6-6 .
1–0
ABCM[1:0]
A and B Comparator Match Control — These bits determine the A and B comparator match mapping as
described in Table 6-7 .
Table 6-6. CDCM Encoding
CDCM Description
00 Match2 mapped to comparator C match....... Match3 mapped to comparator D match.
01 Match2 mapped to comparator C/D inside range....... Match3 disabled.
10 Match2 mapped to comparator C/D outside range....... Match3 disabled.
11 Reserved
(1)
1. Currently defaults to Match2 mapped to inside range: Match3 disabled.
Table 6-7. ABCM Encoding
ABCM Description
00 Match0 mapped to comparator A match....... Match1 mapped to comparator B match.
01 Match0 mapped to comparator A/B inside range....... Match1 disabled.
10 Match0 mapped to comparator A/B outside range....... Match1 disabled.
11 Reserved
(1)
1. Currently defaults to Match0 mapped to inside range: Match1 disabled