Write Buffer
2-8
Note:
Cleaning is not the same as flushing.
The entire D-cache can be invalidated with a single flush D-cache instruction
through the CP15 cache operation register. The D-cache is flushed upon
reset.
If the D-cache is disabled, its content is maintained valid and is accessible
when the cache is reenabled.
2.4.3
Double-Mapped Space
The D-cache works with virtual addresses, and it is assumed that every virtual
address maps to a different physical address. If more than one virtual address
corresponds to the same physical location, the cache cannot maintain its
consistency because each virtual address has a separate entry in the cache
and only one entry is updated on a processor write operation. To avoid any
cache inconsistency, double-mapped virtual addresses must be marked as
uncacheable.
2.5
Write Buffer
The write buffer (WB) increases system performance and can buffer up to
seventeen 32-bit words of data. The MMU attributes B (B_MMU) and C
(C_MMU) (which are part of the TLB descriptor) and the CP15 control register
W bit (W_CP15) control WB behavior.
Clearing W_CP15 and C_CP15 upon reset ensures that all accesses are non-
bufferable until the MMU is enabled. To use the write buffer, you must enable
the MMU. However, you can enable the two functions simultaneously with a
single write to the CP15 control register.
The write buffer is always disabled when the MMU is off.
Clearing bit 3 in the CP15 control register disables the write buffer. Any writes
already in the write buffer complete normally.
It is not possible to abort buffered writes externally, because the s_abort
external signal is ignored and data is simply discarded. Areas of memory that
can generate aborts must be marked as unbufferable in the MMU page tables.
Data Cache / Write Buffer
