Clock Generation and Reset Control Registers
15-60
The MPU reset control 1 register (ARM_RSTCT1) initiates the software reset
to the DSP and to the MPU.
Table 15–13. MPU Reset Control 1 Register (ARM_RSTCT1)
Bit
Name
Value
Description
Type
Reset
Value
15–4
RESERVED
Reading these bits gives undefined values. Writing
to them has no effect.
3
SW_RST
Resets both DSP, MPU, and peripherals (bit is
always read 0):
R/W
0
0
DSP, MPU, and peripheral clock domain enabled
1
DSP, MPU, and peripherals reset—once set to logic
1 by MPU processor, this bit returns to logic 0 once
reset completes.
2
DSP_RST
Resets priority registers (TIPB module), EMIF
configuration registers, and MPUI control logic
(partially) in DSP. This bit is set by external reset
pins and is released by writing a logic 1 in register
(use for MPUI boot).
R/W
0
0
Priority, EMIF configuration registers, and MPUI are
reset.
1
Priority and EMIF configuration registers can be
programmed.
1
DSP_EN
Resets DSP:
R/W
0
0
Resets DSP, excluding configuration setting, and
maintains reset state as long as this bit is asserted
low
1
Enables DSP—after global reset, bit must be set to
a logical 1 to enable DSP.
0
ARM_RST
Resets MPU (bit is always read 0):
R/W
0
0
MPU clock domain enabled
1
MPU reset—once set to logic 1 by MPU processor,
bit returns to logic 0 on next cycles.
Note:
Writing the DSP_EN bit to 0 and ARM_RST bit to 1 together initiate a global software reset.
