UART/Autobaud Control and Status Registers
12-32
The divisor latch low register (DLL) and divisor latch high register (DLH) store
the 16-bit divisor for generation of the baud clock in the baud rate generator.
DLH stores the most significant part of the divisor; DLL stores the least
significant part of the divisor.
Note:
The DLL and DLH can only be written to before sleep mode is enabled (that
is, before IER[4] is set).
Table 12–32. Divisor Latch Low Register (DLL)
Bit
Name
Function
R/W
Reset
Value
7–0
CLOCK_LSB
Used to store the 8-bit LSB divisor value
R/W
0x00
Table 12–33. Divisor Latch High Register (DLH)
Bit
Name
Function
R/W
Reset
Value
7–0
CLOCK_MSB
Used to store the 8-bit MSB divisor value
R/W
0x00
To achieve the required baud rate, you must program DLL/DLH with the
integer part of the divisor value.
Choosing the appropriate divisor value:
UART: Divisor value = Operating Frequency / (16 x Baud Rate)
Just as in autobaud mode, the input frequency of the UART modem must be
fixed to the operating frequency (here 12 MHz; no CLKSEL bit setting) and the
the OSC_12M_SEL bit must be set to be able to reach desired baud rate. Set-
ting OSC_12M_SEL to 1 enables turning on the 6.5 division factor. For
instance, 12 MHz/16/6.5 = 115200 bps; in case OSC_12M_SEL is not set,
reached baud rate is either 12 MHz/16/6 or 12 MHz/16/7, which are out of
permitted tolerance.
