Camera Interface
7-9
MPU Public Peripherals
Figure 7-8. FIFO Buffer Parts
CAMERA
32
32
TIPB
DMA_REQ
Buffering Word y
Block Word 1
Buffering Word Q
Buffering Word I
When the threshold value is set to 0, the interrupt is generated immediately.
This is the equivalent of the threshold always being exceeded regardless of
whether any data is present in the FIFO.
7.2.1.6
Clock Divider
The clock divider takes the internal 12-MHz clock source or the 48-MHz source
from DPLL to generate the external clock CAM.EXCLK. The division factor is
programmable in the clock control register through FOSCMOD (see
Table 7-1).
Table 7-1. Clock Ratios
Ratio
CAM.EXCLK
From 12 MHz
From 48 MHz
1
12 MHz
-
1/2
6 MHz
24 MHz
1/5
-
9.6 MHz
1/6
-
8 MHz
A request is automatically generated to wake up the DPLL when 48 MHz is
needed. The switch is performed when the 48-MHz signal is stable.
It is assumed that the switch is made when CAM.EXCLK is disabled (glitch
protection).
