OMAP5910 Local Bus
14-93
Universal Serial Bus Host
14.7 OMAP5910 Local Bus
The OMAP5910 local bus supports both slave and master peripherals. This
bus allows the MPU, DSP, and DMA controller to access local bus slave
peripherals and allows local bus master peripherals to move data to and from
system memory.
The OMAP5910 device does not implement any local bus slave peripherals.
The local bus interface of the OMAP5910 USB host controller implements a
local bus master peripheral which enables the USB host controller to access
system memory via the OMAP5910 local bus and the OMAP5910 traffic
controller.
14.7.1 LB Register Descriptions
Table 14–38 lists the registers associated with local bus (LB) control and
status. Table 14–39 through Table 14–47 describe specific register bits.
The LB_CLOCK_DIV register has a direct impact on the ability of the USB host
controller to access OMAP5910 system memory. The remaining OMAP5910
local bus control and status registers have no direct effect, because they con-
trol MPU, DSP, and DMA controller accesses to slave peripherals addressed
via local bus and there are no slave peripherals on the OMAP5910 local bus.
The local bus memory management unit and its registers are discussed
separately in section 14.8, OMAP5910 Local Bus MMU
.
Table 14–38. Local Bus Control Registers
Name
Description
R/W
Size†
Address
LB_MPU_TIMEOUT
LB MPU time-out
R/W
32
FFFE:C100h
LB_HOLD_TIMER
LB hold timer
R/W
32
FFFE:C104h
LB_PRIORITY_REG
LB priority
R/W
32
FFFE:C108h
LB_CLOCK_DIV
LB clock divider
R/W
32
FFFE:C10Ch
LB_ABORT_ADD
LB abort address
R
32
FFFE:C110h
LB_ABORT_DATA
LB abort data
R
32
FFFE:C114h
LB_ABORT_STATUS
LB abort status
R
32
FFFE:C118h
LB_IRQ_OUTPUT
LB IRQ output
R/W
32
FFFE:C11Ch
LB_IRQ_INPUT
LB IRQ input
R
32
FFFE:C120h
† Access to these registers must be by 32-bit reads or 32-bit writes. Use of other access sizes may result in undefined operation.
