UART/IrDA Functional Description
12-92
Figure 12–19. Transmit FIFO IT Request Generation
Number
of
spaces
Programmable FIFO threshold
Transmit FIFO level
Zero byte
time
Interrupt request
time
Interrupt request
Active low
Full level
In transmit mode, an interrupt request is automatically asserted when FIFO is
empty. This request is deasserted when the FIFO crossed the threshold level.
The interrupt line is deasserted until a sufficient number of elements has been
transmitted to go below FIFO threshold.
12.9.5 FIFO Polled Mode Operation
In FIFO polled mode (FCR [0] = 0 with relevant interrupts disabled via interrupt
enable register (IER)), the status of the receiver and transmitter can then be
checked by polling the line status register (LSR). This mode is an alternative
to the FIFO interrupt mode of operation, where the status of the receiver and
transmitter is automatically known by means of interrupts sent to the host
(MPU or DSP).
