UART/IrDA Control and Status Registers
12-63
UART Devices
Table 12–51. SIR Mode Line Status Register (SIR_LSR) (Continued)
Bit
Reset
Value
R/W
Function
Value
Name
0
RX_FIFO_E
0
At least one data character in the
RX_FIFO
R
1
1
No data in the receive FIFO
When the LSR is read, LSR[4:2] reflect the error bits [FL, CRC, ABORT] of the
frame at the top of the STATUS FIFO (next frame status to be read). In SIR
mode, the LSR bits [4:2] reflect the same values as the SFLSR bits [3:1].
Table 12–52. Supplementary Status Register (SSR)
Bit
Name
Value
Function
R/W
Reset
Value
7–2
–
Reserved
R
000000
1
RX_CTS_DSR_WAKE
_UP_STS
0
No falling edge event on RX, CTS and
DSR
R
0
1
A falling edge occurred on RX, CTS or
DSR.
0
TX_FIFO_FULL
0
TX FIFO not full
R
0
1
TX FIFO full
Note:
Bit 1 is reset only when SCR[4] is reset to 0.
