Clock Generation and Reset Control Registers
15-78
This is the control register for the 48-MHz DPLL.
The reset multiply and divide settings are fixed for x4 operation to achieve a
48-mHz clock. The DPLL must always remain enabled when it is used to gen-
erate the 48-mHz clock for USB, UARTs, or other peripherals
Writing to the DPLL control register (DPLL_CTRL_REG)
causes the DPLL to
switch immediately to the bypass mode if not in idle state. If the PLL_ENABLE
bit of the control register is set, it begins its sequence to enter the locked mode.
This prevents being able to change the multiple or divide values without
reentering the DPLL lock sequence.
Table 15–37. DPLL Control Register (DPLL_CTRL_REG)
Bit
Name
Description
Type
Reset
Value
15–14
RESERVED
This bit is reserved and set to 0.
13
IOB
Initialize on break. When high, DPLL switches to bypass
mode and starts a new locking sequence if DPLL core
ever indicates that it lost lock. When set low, DPLL
continues to output synthesized clock, even if core
indicates it has lost lock, but BREAKLN is active low.
The power-on value is 1.
R/W
1
12
RESERVED
This bit is reserved and set to 0.
11–7
PLL_MULT(4:0)
This bit is reserved and always written to its reset value.
R/W
0x0
6–5
PLL_DIV(1:0)
This bit is reserved and always written to its reset value.
R/W
0x0
4
PLL_ENABLE
Setting PLL_ENABLE bit to 1 requests DPLL to enter
LOCK mode. It enters lock mode only after it has
synthesized desired frequency. Clearing bit to 0 causes
DPLL to switch back to the bypass mode.
R/W
1
3–2
BYPASS_DIV(1:0)
This bit is reserved and always written to its reset value.
R/W
0x0
1
BREAKLN
When BREAKLN = 0 , DPLL has broken lock for some
unknown reason. If and when lock condition is restored
or a write to control register occurs, BREAKLN returns to
1
.
R
0x1
0
LOCK
When LOCK = 1, DPLL is in lock mode and clkout is
desired synthesized clock frequency. When LOCK = 0,
DPLL is in bypass mode and clkout contains a divided
down output clock.
R
0x0
