Registers
5-46
Table 5–13. DMA Channel Control Register (DMA__CCR) (Continued)
Bit
Reset
Value
Type
Description
Value
Name
8
AUTO_INIT
Autoinitialization at the end of the transfer
RW
0
0
The channel stops at the end of the current transfer.
1
When the current transfer is complete, the channel
automatically reinitializes itself and starts a new
transfer.
There are two ways to stop a channel while it is in
autoinitialization mode:
-
Write a 0 to the DMA_CCR EN bit; the channel
immediately stops.
-
Write a 0 to the DMA_CCR AUTO_INIT bit; the
channel completes the current transfer and stops.
7
EN
Enable
This bit is used to enable/disable the transfer in the
DMA channel.
RW-
RST
0
0
The transfer stops, and it is reset.
1
The transfer starts.
This bit is automatically cleared by the DMA once the
transfer is accomplished. Clearing of this bit by the
DMA has the priority over write by the processor. If
both simultaneously occur, the processor write is
discarded.
6
PRIO
Channel priority
RW
0
0
The channel has low priority level.
1
The channel has high priority level.
