DSP Memory
3-13
DSP Subsystem
Figure 3–6. DSP Memory Space
00_0000
01_0000
02_8000
FF_FFFE
PDROM
32K-byte
masked ROM
Reset vectors
FF_8000
01_4000
00_8000
00_0000
DARAM
64K bytes–0X100 bytes
8 blocks
(Table A)
SARAM
96K bytes
12 blocks
External to
NMI vectors
Emu/test vectors
L2 peripherals
TC abort
Bus error
FF_FF00
7F_C000
7F_FF80
7F_FFFF
Byte address
Word address
daram0
00 _0000
00_1000
Byte address
WORD Addr
32 interrupt
vectors
The TMS320C55x DSP has 24-bit unified address space for both data and
* Program accesses are specified and displayed as byte addresses.
* Data objects are word addressable and are specified by 16-bit
* The DMA controller references byte addresses.
To access control and data registers associated with various OMAP5910
daram1
00 _2000
00_2000
daram2
00 _4000
00_3000
daram3
00 _6000
00_4000
daram4
00 _8000
00_5000
daram5
00 _A000
00_6000
daram6
00 _C000
00_7000
daram7
00 _E000
00 _0000
saram0
01 _0000
00_9000
Byte address
WORD Addr
saram1
01 _2000
00_A000
saram2
01 _4000
00_B000
saram3
01 _6000
00_C000
saram4
01 _8000
00_D000
saram5
01 _A000
00_E000
saram6
01 _C000
00_F000
saram7
01 _E000
00_8000
saram8
02 _0000
01_1000
saram9
02 _2000
01_2000
saram10
02 _4000
01_3000
saram11
02 _6000
01_0000
Word address
Word address
EMIF
DMA
I-Cache
Timer1
Timer2
Timer3
WD_Timer
CLKM2
L2 Int handler
00000
00800
01000
01800
02000
02800
03000
03800
04000
04800
05000
05800
06000
06800
07000
07800
08000
08800
09000
09800
0A000
0A800
0B000
0B800
0C000
0C800
0D000
0D800
0E000
0E800
0F000
0F800
10000
10800
11000
11800
12000
I/O Space
00800
00400
00000
00C00
01000
01400
01800
00C00
02000
02800
02400
02C00
03000
03400
03800
03C00
04000
04800
04400
04C00
05000
05400
05800
05C00
06000
06800
06400
06C00
07000
07400
07800
07C00
08000
08400
08800
08C00
09000
Table A DARAM block boundaries
Table B SARAM block boundaries
UART3
Mailbox
DSP MPUI register
12800
13000
13800
14000
14800
15000
15800
16000
16800
17000
17800
18000
18800
19000
19800
1A000
1A800
1B000
1B800
1C000
1C800
1D000
1D800
1E000
1E800
1F000
1F800
09400
09800
09C00
0A000
0A800
0A400
0AC00
0B000
0B400
0B800
0BC00
0C000
0C800
0C400
0CC00
0D000
0D400
0D800
0DC00
0E000
0E800
0E400
0EC00
0F000
0F400
0F800
0FC00
GPIO
program references.
word addresses.
peripherals, the DSP uses 16-bit I/O space. This space is referenced
UART1,2,3 shading SW
TIPB bridge
McBSP1
MCSI2
MCSI1
McBSP3
by using appropriate I/O access qualifiers with load or store instructions.
MMRs
00_0080
00_0100
UART1
UART2
DSP subsystem
16 MB
mapped by
DSP MMU
into MPU 32-bit
address space
Restrictions apply for data objects spanning 64K-word (128K-byte) boundaries.
See TMS320C55x DSP CPU Reference Guide (SPRU371).
I-Cache
Byte
Word
Byte
Word
Note:
Byte addresses 0xFF8000-0xFFFFFF map to PDROM for mpnmc = 0; otherwise, this range is mapped externally
.