Memory Interfaces
4-25
Memory Interface Traffic Controller
mode is recommended only for 16-bit accesses since the OMAP5910 EMIFS
keeps chip-select and write enable active between the two accesses gener-
ated by one 32-bit access to EMIFS. While nothing prevents the use of 32-bit
accesses in DPRAM interface mode, avoid it if address must be known valid
while write enable is active.
4.3.3
External Memory Interface Fast
The EMIFF can interface with synchronous DRAM (SDRAM). The interface
directs all the transactions to the SDRAM device. The bus width is 16 bits.
Table 4–6 shows the EMIFF signal list.
Table 4–6. External Memory Interface Fast Signal List
Signal Name
I/O
Bus
Description
SDRAM.A[12:0]
O
12 - 0
SDRAM address bus
SDRAM.D[15:0]
I/O
15 - 0
Data from SDRAM
SDRAM.CLK
I/O
–
Clock to SDRAM
SDRAM.BA[1:0]
O
1 - 0
SDRAM bank select
SDRAM.CKE
O
–
SDRAM clock enable
SDRAM.RAS
O
–
SDRAM RAS
SDRAM.CAS
O
–
SDRAM CAS
SDRAM.WE
O
–
SDRAM write enable
SDRAM.DQML
O
–
Lower byte 3-state
SDRAM.DQMU
O
–
Upper byte 3-state
4.3.3.1
EMIFF Priority Handler
This memory interface has two software-selectable priority algorithms for
resolving simultaneous access requests: least recently used and dynamic
priority. The priority scheme is shared with the EMIFS and IMIF and is set in
the OMAP5910 configuration registers (bit 20, LRU_SEL in
FUNC_MUX_CTRL_0). See Chapter 6, MPU Private Peripherals, for details
on configuration registers.
-
Least recently used
J
A round-robin arbitration scheme. The highest priority requestor is the
one that least recently accessed the memory.
