Texas Instruments OMAP5910, Technical Reference Manual

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Clock Generation and Reset Control Registers
15-73 Clock Generation and System Reset Management
Table 15–26 lists the ULPD registers. Table 15–27 through Table 15–41
describe the register bits.
Bit Width: 32
Table 15–26. ULPD Registers – MPU Base Address: FFFE:0800
Name Descriptions R/W Size Offset
Reset
Value
COUNTER_32_LSB Lower value of number of
ticks from 32-kHz clock R 16 bits x00 0x0001
COUNTER_32_MSB Upper value of number of
ticks from 32-kHz clock R 16 bits x04 0x0000
COUNTER_HIGH_FREQ_LSB Lower value of number of
ticks from high frequency
clock R 16 bits x08 0x0001
COUNTER_ HIGH_FREQ _MSB Upper value of number of
ticks from high frequency
clock R 16 bits x0C 0x0000
GAUGING_CTRL_REG Drives gauging functionality R/W 16 bits 0x10 0x0000
IT_STATUS_REG Interrupt status register R 16 bits 0x14 0x0000
Reserved 8 bits 0x18 0x01
Reserved 8 bits 0x1C 0x01
Reserved 8 bits 0x20 0x01
SETUP_ANALOG_CELL3_ULPD1_REG Number of 32-kHz clocks to
wake up R/W 16 bits 0x24 0x03FF
Reserved 8 bits 0x2C 0x01
Reserved 8 bits 0x28 0x01
CLOCK_CTRL_REG Manages clock output and
inactive values R/W 16 bits 0x30 0x0000
SOFT_REQ_REG Manage software clock
requests R/W 16 bits X34 0x0000
COUNTER_32_FIQ_REG Number of 32-kHz clocks to
delay active modem shut
down signal after receiving
an active EXT_FIQ signal R/W 16 bits X38 0x0001
DPLL_CTRL_REG 48-MHz DPLL R/W 16 bits X3C 0x2211
STATUS_REQ_REG Status of hardware requests R 16 bits 0x40 U