Clock Generation and Reset Control Registers
15-63
Clock Generation and System Reset Management
Table 15–15. MPU System Status Register (ARM_SYSST) (Continued)
Bit
Reset
Value
Type
Description
Value
Name
0
DSP_WDRST
Indicates whether or not reset has been asserted
due to a DSPs timer/watchdog underflow. This bit is
cleared to logic 0 upon an reset pulse asserting at
CHIP_nRESET signal, or by writing it to logic 0.
This bit cannot be written to logic 1 from peripheral
bus interface:
R/C
0
0
DSP timer/watchdog underflow has not occurred.
1
DSP timer/watchdog underflow has generated
reset.
Table 15–16 lists the clocking schemes for the MPU system status register
(ARM_SYSST).
Table 15–16. Clocking Schemes for OMAP5910
CLOCK_SELECT (2)
CLOCK_SELECT (1)
CLOCK_SELECT (0)
CLOCK SCHEME
0
0
0
Fully synchronous
0
0
1
Reserved
0
1
0
Synchronous scalable
0
1
1
Reserved
1
x
x
Reserved
