Clock Generation
15-19
Clock Generation and System Reset Management
15.2.7 Clock Distribution and Synchronization
When any of the clock domains are running at different frequencies with
respect to each other, FIFOs are used to buffer data being transferred between
domains (see Figure 15–8). This is necessary to ensure that data being sent
from a fast domain is buffered as a slow domain receives it. This buffering intro-
duces latencies as data is passed between domains. Thus, this buffering can
be bypassed if it is not needed (that is, when domains are running at the same
speeds).
-
For the fully synchronous clocking scheme, MPU_CK = DSPMMU_CK =
TC_CK; the FIFO logic is bypassed between TC and MPU, TC and
DSPMMU.
-
For the synchronous scalable clocking scheme, FIFO logic is used for both
processors.
Note:
TC_CK clock must be slower than or equal to the MPU_CK and DSP MMU
clock speed.
Figure 15–8. OMAP5910 Clock Distribution and Synchronization
Clock
generator
DSP
MPU
MPU peripherals, GPIO
DSP peripherals
UART, GPIO
FIFO
FIFO
Clock
gating
Traffic
controller (TC)
CLKIN
DSP
MMU
TC clock domain
DSP clock domain
MPU clock domain
MPU_CK
DSPMMU_CK
TC_CK
TC_CK
