Clock Generation
15-16
After reset, the highest frequency option (CK_GEN2 divided by 1) is selected
for GPIO and DSPPER clocks. The software application program can alter
these divisors at any time during operation by writing to the GPIODIV or
DSP_PERDIV bits in the DSP clock control register (DSP_CKCTL).
The clock generator output (CK_GEN2) delivers a 50% duty cycle to the DSP
subsystem clock distribution module (CLKM2). This module provides addition-
al clock scaling, routing, and idle/reset control to the DSP to individual
components in the DSP clock domain.
The CK_GEN2 clock works in conjunction with the idle and wake-up control
logic to produce the DSP_CK clock signal that drives the DSP subsystem, the
DSP MMU, and the DSP interrupt modules.
At reset, the CK_GEN2 is in the bypass mode, so it supplies (CLKM2) a clock
of the same 12-MHz frequency as CLKIN. After the global reset period, the
MPU application program can change the clock frequency through the
CK_GEN2 control register.
DSP_CK is enabled at reset until the DSP is in reset state. The EN_DSPCK
bit (located in the clock control register ARM_CKCTL) allows the MPU to turn
off the DSP_CK while the DSP is held in a reset state.
A free-running counter/divider receives the CK_GEN2 signal and makes avail-
able four taps where a 50% duty-cycle clock and the clock
divided by 1, 2, 4, and 8 can be selected. A multiplexer set through the DSPDIV
bits in the clock control register (ARM_CKCTL) selects the clock frequency
that applies to the DSP clock domain.
At reset, the higher frequency (divide by 1) is selected. The software applica-
tion program (accessing the control register file) can change the divider ratio
by writing to the DSPDIV [1 – 0] bits at any time while the OMAP5910 device
is running. A synchronization mechanism is implemented to remove any
spikes while the clock frequency is changing (disable the clock first, change
the DSPDIV bits, and then enable the clock).
