UART/IrDA Control and Status Registers
12-62
Table 12–51. SIR Mode Line Status Register (SIR_LSR)
Bit
Name
Value
Function
R/W
Reset
Value
7
THR_EMPTY
0
Transmit hold register is not empty.
R
1
1
Transmit hold register is empty. The
processor can now load up to 64 bytes of
data into the THR if the TX FIFO is
enabled.
6
STS_FIFO_FULL
0
Status FIFO not full
R
0
1
Status FIFO full
5
RX_LAST_BYTE
0
Did not receive last byte of a frame from
the FIFO
R
0
1
Received last byte from FIFO. This bit is
set when the last byte of a frame is read.
Used to determine the frame boundary.
Cleared by first reading the last received
byte, then reading the SIR_LSR register.
4
FRAME_TOO_LONG
0
No frame-too-long error in frame
R
0
1
Frame-too-long error in the frame at the
top of the STATUS FIFO next character to
be read. This bit is set to 1 when a frame
exceeding the maximum length (set by
RXFLH and RXFLL registers) has been
received. When this error is detected,
current frame reception is terminated.
Reception is stopped until the next START
flag is detected.
3
ABORT
0
No abort pattern error in frame
R
0
1
Abort pattern received
2
CRC
0
No CRC error in frame
R
0
1
CRC error in the frame at the top of the
STATUS FIFO (next character to be read)
1
STS_FIFO_E
0
Status FIFO not empty
R
1
1
Status FIFO empty
