Traffic Controller Memory Interface Registers
4-52
Table 4–20. EMIF Fast Interface SDRAM MRS Register—Default (EMIFF_MRS)
Bit
Field
Value
Description
Access
Reset
Value
31–10
Reserved
Read is undefined. Writes must be zero.
R
All 0
9
WBST
Write burst must be 0 (burst write same as burst
read).
R/W
0
8–7
Reserved
Read is undefined. Writes must be zero.
R/W
00
6–4
CASL
CAS latency:
R/W
011
001
CAS latency = 1
010
CAS latency = 2
011
CAS latency = 3 (default at reset)
3
S/I
Serial = 0. This bit must be 0.
Interleave = 1. Reserved. Do not use this setting.
R/W
0
2–0
PGBL
Specifies page burst length to be programmed into
SDRAM MRS configuration register. The length must
always be programmed as full-page burst length
(111). (This length is not necessarily the burst length
at which the EMIFF operates, but rather a setting for
the SDRAM MRS register.)
R/W
111
Note:
When the CONF_MOD_EMRS_CTRL bit field (bit 13) of the OMAP5910 control register (MOD_CONF_CTRL_0) is
set, the device reconfigures bank settings to write out the EMIFF_MRS register as EMRS commands (see
Table 4–21).
