DSP Interrupt Interface
8-27
DSP Private Peripherals
When the edge-registration flip-flop is cleared by the asynchronous reset, two
DSP_INTH_CK clock periods must expire before another negative edge tran-
sition can be registered. Thus successive negative transitions must be a mini-
mum of six DSP_INTH_CK clock periods apart in time to be ensured of being
recognized as two separate incidents. This minimal time does not take into
account the processing time of the interrupts once recognized by the DSP
processor, and this time must be taken into account to derive the minimum time
between interrupts from a system perspective.
Figure 8–5. Interrupt Channel Implementation
Interrupt
channel
XIRQ(N)
SCL
D
Q
SCL
D
Q
SCL
D
Q
SCL
D
Q
Q
ACL
D
Q
D
Q
D
Q
D
Q
D
Q
XIRQOUT
(N)
CLKOUT
Asynchronous
clear
Level-
sensitive
interrupt
Edge-triggered interrupt
Interrupt(N) software-executed
Clear command
Synchronous clear
Interrupt(N) edge-triggered
enable