Power Management
15-33
Clock Generation and System Reset Management
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When the MPU idle mode entry 1 register (ARM_IDLECT1)
WKUP_MODE field = 0, the OMAP5910 device does not wake up, even
if one of the above wake-up conditions occurs, until the CHIP_nWAKEUP
goes active.
J
MPU interrupt
J
DSP interrupt
J
Internal local bus activity (TCLB_EN signal = 1)
In chip idle, if this signal is inactive (high), the OMAP5910 device does not
wake up (prevent from waking up), even if one of the above wake-up
conditions has occurred. This signal has no effect when the OMAP5910
device is not in chip idle. When the MPU idle mode entry 1 register
(ARM_IDLECT1) WKUP_MODE = 0, the OMAP5910 device does not
wake up, even if one of the above wake-up conditions has occurred.
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WAKEUP_nREQ: request to the ULPD to wake up the chip. This signal is
looked at only when the CHIP_IDLE signal is high. Note that
WAKEUP_nREQ is asserted by OMAP whenever there any wake-up
condition occurs, even when OMAP is not in CHIP_IDLE.
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FLASH.RP and SDRAM.CKE: Power control for external devices (for
example, flash and SDRAM)
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Power-on reset: Must be valid until power and input clock are stable
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CHIP_IDLE: Chip idle mode. Indicates that all internal clocks are stopped.
This internal signal is active regardless the state of the external wake-up
control feature. This pin is asserted (high) when all DPLL ACKs are
returned and all the peripherals using CK_REF are disabled.
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TCLB_EN: TC local bus enable, enables restart of the clock to the TC
when the idle mode is set.
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DSP interrupts (internal signal is DSP_nIRQ): Interrupt request from the
DSP interrupt handler. Asserts when an unmasked interrupt has been
asserted.
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MPU IRQ (internal signal is nIRQ_SET): Interrupt request from the MPU
interrupt handler. Asserts when an unmasked interrupt has been asserted.
When MPU is awake, must remain low until MPU clock restart.
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DSP_IDLE—DSP idle command
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MPU_IDLE—MPU idle command
