Memory Interfaces
4-30
Caution: Self-Refresh Mode
When the EMIFF SDRAM is in self-refresh mode, the EMIFF does
not respond to TIPB requests including MRS writes. To respond,
the SLFR bit must be cleared by firmware. Writes to TC registers
which would normally cause EMIFF to perform an action have no
effect while EMIFF is in self-refresh mode. If an MRS write is
attempted while EMIFF is in self-refresh mode, there is a pending
MRS request. This prevents the traffic controller from idling and
therefore prevents the device from entering deep sleep mode. The
MRS request is not serviced until the SLFR bit is cleared.
4.3.3.6
SDRAM Clock Disable
The EMIF fast SDRAM clock signal (SDRAM.CLK) is disabled using these
steps:
1) Set the PDE bit field of the EMIF slow interface configuration register.
2) Set one (or both) of the following bit fields in the EMIF fast SDRAM
configuration register 1
a) Set the SLRF to place the SDRAM into self-refresh mode
b) Set the PWD to place the SDRAM into power-down mode
3) Set the CLK bit field of the EMIF fast interface SDRAM configuration
register 1 to stop the clock
4.3.3.7
Endianism Conversion Control
The traffic controller registers include a register to control endianism
conversion in the DSP memory management unit. For details, see Table 4–25,
Endianism Register (ENDIANISM).
4.3.3.8
SDRAM Access Timing Diagrams
Figure 4–8 through Figure 4–18 show the SDRAM timing diagrams. Burst
accesses shown here might not be achievable by all initiators of EMIFF trans-
actions. See Section 4.3.3.2 for more detail on bursting behavior.
