UART/Autobaud Control and Status Registers
12-24
Table 12–18. Line Control Register (LCR) (Continued)
Bit
Reset
Value
R/W
Function
Value
Name
1–0
CHAR_LENGTH
Specifies the word length to be
transmitted or received.
R/W
00
00
5 bits
01
6 bits
10
7 bits
11
8 bits
Note:
As soon as LCR[6] is set to 1, the RX line is forced to 0 and remains in this state as long as LCR[6] = 1.
Table 12–19. UART Mode Line Status Register (LSR)
Bit
Name
Value
Function
R/W
Reset
Value
7
RX_FIFO_STS
0
Normal operation
R
0
1
At least one parity error, framing error or
break indication in the receiver FIFO. Bit 7 is
cleared when no more errors are present in
the FIFO.
6
TX_SR_E
0
Transmitter hold and shift registers are not
empty.
R
1
1
Transmitter hold and shift registers are empty.
5
TX_FIFO_E
0
Transmit hold register is not empty.
R
1
1
Transmit hold register is empty. The
processor can now load up to 64 bytes of
data into the THR if the TX FIFO is enabled.
4
RX_BI
0
No break condition
R
0
1
A break was detected while the data being
read from the RX FIFO was being received
(i.e., RX input was low for one character time
frame).
