LCD Controller Registers
11-36
11.8.3 LCD Timing 1 Register (LcdTiming1)
The LCD timing 1 register contains four bit fields that are used as modulus
values for a collection of down counters, each of which performs a different
function to control the timing of several of the LCD lines.
Table 11–19 shows the location of the bit fields located in LCD timing 1 register
(LCDTiming1) and provides bit descriptions. The LCD controller must be dis-
abled (LCDEN = 0) when changing the state of any field within this register. The
reset state of all bit fields is unknown and must be initialized before
enabling the LCD.
Table 11–19. LCD Timing 1 Register (LcdTiming1)
Bit
Name
Description
Reset
Value
31–24
VBP
Vertical back porch
Value (0
–
255) used to specify number of line clock periods to add to the
beginning of a frame before the first set of pixels is output to the display. The
line clock transitions during the insertion of the extra line clock periods.
0
23–16
VFP
Vertical front porch
Value (0
–
255) used to specify number of line clock periods to add to the end
of each frame. The line clock transitions during the insertion of the extra line
clock periods.
0
15–10
VSW
Vertical synchronization pulse width
In active mode (LCDTFT = 1), encoded value (1
–
64) used to specify
number of line clock periods to pulse the LCD.VS pin at the end of each
frame after the end of frame wait (VFP) period elapses. Frame clock used as
VSYNC signal in active mode (program to value minus one).
In passive mode (LCDTFT = 0), encoded value (1
–
64) used to specify
number of extra line clock periods to insert after the vertical front porch
(VFP) period has elapsed. The width of LCD.VS is not effected by VSW in
passive mode and that line clock transitions during the insertion of the extra
line clock periods (program to value minus one).
0
9–0
LPP
Lines per panel
Encoded value (1
–
1024) used to specify number of lines per panel. It
represents the total number of lines on the LCD (program to value minus
one).
0
