UART/IrDA Control and Status Registers
12-57
UART Devices
Table 12–47. FIFO Control (FCR) Register (Continued)
Bit
Reset
Value
R/W
Function
Value
Name
3
DMA_MODE
0
DMA_MODE 0 (no DMA)
W
0
1
DMA_MODE 1 (UART_nDMA_REQ0 in TX,
UART_nDMA_REQ1 in RX)
This register is considered if SCR0 = 0.
2
TX_FIFO_CLEAR
0
No change
W
0
1
Clears the transmit FIFO and resets its
counter logic to zero. Returns to zero after
clearing FIFO.
1
RX_FIFO_CLEAR
0
No change
W
0
1
Clears the receive FIFO and resets its
counter logic to zero. Returns to zero after
clearing FIFO.
0
FIFO_EN
0
Disables the transmit and receive FIFOs
W
0
1
Enables the transmit and receive FIFOs
Notes:
1) Bits 4 and 5 can only be written when EFR[4] = 1.
2) Bits 0 to 3 can be changed only when baud clock is not running (DLL and DLH set to 0).
3) See Table 12–36 for FCR[5:4] setting restriction when SCR[6] = 1.
4) See Table 12–37 for FCR[7:6] setting restriction when SCR[7] = 1.
