Memory Interfaces
4-19
Memory Interface Traffic Controller
4.3.2.6
Asynchronous Page Mode Read Operation
The asynchronous read operation (page mode) is similar to the asynchronous
read, except that the number of wait states is different between the first access
and the subsequent accesses within the page.
This mode of operation is selected by programming the following fields of the
EMIF slow chip-select configuration registers (see Table 4–13, EMIF Slow
Chip-Select Configuration Registers).
-
RDMODE selects the memory type and number of words per page for
page mode devices; supported values for words per page are 4, 8, or 16.
-
RDWST sets the delay to insert prior to latching the first data word read
from a page (range 0-15). The resulting delay is equal to (RDWST+2) x
EMIFS_ref. This is represented by N cycles in Figure 4–4 and Figure 4–5.
When crossing a page boundary, as in Figure 4–5, the RDWST parameter
is used again for the first access on the new page.
-
PGWST sets the delay between subsequent words in the page (range
0-15). The resulting delay is equal to (PGWST+1) x EMIFS_ref. This is
represented by P cycles in Figure 4–4 and Figure 4–5.
-
BW defines the word length of the access, which is equal to the memory
data bus width.
As in asynchronous mode, device interface signals are referenced to the inter-
nal EMIFS reference clock, which is divided from the TC clock using FCLKDIV
in the EMIF slow interface configuration register. The FLASH.CLK signal is not
externally driven in asynchronous page operating mode.
Figure 4–4 shows typical timing for an asynchronous page mode 8x16-bit read
operation on a 16-bit width device with RDWST = 2, PGWST = 0,
FCLKDIV = 01, and RDMODE = 2.
Figure 4–5 shows typical timing for an asynchronous page mode 8x16-bit read
with page crossing on a 16-bit width device with RDWST = 2, PGWST = 0,
FCLKDIV = 01, and RDMODE = 2.
