Clock Generation and Reset Control Registers
15-56
Table 15–10. MPU Idle Mode Entry 1 Register (ARM_IDLECT1) (Continued)
Bit
Reset
Value
Type
Description
Value
Name
6
IDLIF_ARM
Enables local-bus, peripheral bridge, system DMA
controller, and traffic controller of the MPU
subsystem to enter idle mode whenever the MPU
sets SET_IDLE bit or executes a wait-for-interrupt
instruction:
R/W
0
0
Clocks TIPB_CK, DMA_CK, and TC_CK remain
active when the MPU enters idle mode.
1
Clocks TIPB_CK, DMA_CK, and TC_CK are
stopped in conjunction with the MPU clock when
idle mode is entered.
5–3
RESERVED
Reserved. To prevent errant behavior, always write
this bit as 0.
R/W
0
2
IDLPER_ARM
Selects idle entry mode for peripheral clock
(MPUPER_CK)
R/W
0
0
Clock remains active when MPU enters idle mode.
1
Clock stopped in conjunction with MPU idle mode
entry.
1
IDLXORP_ARM
Selects idle entry mode for 32-k or gp timer (MPU
TIPB) and peripheral clock (MPUXOR_CK):
R/W
0
0
OS timer and MPUXOR_CK clock remain active
when MPU enters idle mode.
1
OS timer and MPUXOR_CK clock are stopped in
conjunction with MPU clock when idle mode is
entered.
0
IDLWDT_ARM
Selects idle entry mode for internal timer/watchdog
connected to MPU peripheral bus:
R/W
0
0
Clock supplied to timer/watchdog remains active
when MPU enters idle mode.
1
Timer/watchdog clock stopped in conjunction with
MPU clock when idle mode is entered.
Note:
When the timer/watchdog is configured as watchdog timer, the clock is never shutdown, regardless of the value of the
IDLWDT_ARM bit.
